Methods and apparatus to provide electrical shielding for integrated circuit packages using a thermal interface material

ABSTRACT

Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.

FIELD OF THE DISCLOSURE

This disclosure relates generally to integrated circuit (IC) packagesand, more particularly, to methods and apparatus to provide electricalshielding for IC packages using a thermal interface material.

BACKGROUND

In IC packages, a thermal interface material (TIM) is sometimes used tothermally couple components of the package. Additionally, a TIM can beused to dissipate heat between components of the package, such asbetween layers of semiconductor materials, metals, and/or dielectrics.In recent years, there has been interest in using a liquid metal TIM(LM-TIM).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of an example IC package constructed in accordancewith teachings disclosed herein.

FIG. 2 is a cross-sectional view of the example IC package of FIG. 1taken along line 2-2.

FIG. 3 is an enlarged view of a portion of the example IC package ofFIG. 1 corresponding to region A shown in FIG. 2 .

FIG. 4 is a plan view of another example IC package constructed inaccordance with teachings disclosed herein.

FIG. 5 is a cross-sectional view of the example IC package of FIG. 4taken along line 5-5.

FIG. 6 is a plan view of another example IC package constructed inaccordance with teachings disclosed herein.

FIG. 7 is a cross-sectional view of the example IC package of FIG. 6taken along line 7-7.

FIG. 8 is a cross-sectional view of another example IC packageconstructed in accordance with teachings disclosed herein.

The figures are not necessarily to scale. Instead, the thickness of thelayers or regions may be enlarged in the drawings. Although the figuresshow layers and regions with clean lines and boundaries, some or all ofthese lines and/or boundaries may be idealized. In reality, theboundaries and/or lines may be unobservable, blended, and/or irregular.In general, the same reference numbers will be used throughout thedrawing(s) and accompanying written description to refer to the same orlike parts. As used herein, unless otherwise stated, the term “above”describes the relationship of two parts relative to Earth. A first partis above a second part, if the second part has at least one part betweenEarth and the first part. Likewise, as used herein, a first part is“below” a second part when the first part is closer to the Earth thanthe second part. As noted above, a first part can be above or below asecond part with one or more of: other parts therebetween, without otherparts therebetween, with the first and second parts touching, or withoutthe first and second parts being in direct contact with one another.Notwithstanding the foregoing, in the case of a semiconductor device,“above” is not with reference to Earth, but instead is with reference toa bulk region of a base semiconductor substrate (e.g., a semiconductorwafer) on which components of an integrated circuit are formed.Specifically, as used herein, a first component of an integrated circuitis “above” a second component when the first component is farther awayfrom the bulk region of the semiconductor substrate than the secondcomponent. As used in this patent, stating that any part (e.g., a layer,film, area, region, or plate) is in any way on (e.g., positioned on,located on, disposed on, or formed on, etc.) another part, indicatesthat the referenced part is either in contact with the other part, orthat the referenced part is above the other part with one or moreintermediate part(s) located therebetween. As used herein, connectionreferences (e.g., attached, coupled, connected, and joined) may includeintermediate members between the elements referenced by the connectionreference and/or relative movement between those elements unlessotherwise indicated. As such, connection references do not necessarilyinfer that two elements are directly connected and/or in fixed relationto each other. As used herein, stating that any part is in “contact”with another part is defined to mean that there is no intermediate partbetween the two parts.

Unless specifically stated otherwise, descriptors such as “first,”“second,” “third,” etc. are used herein without imputing or otherwiseindicating any meaning of priority, physical order, arrangement in alist, and/or ordering in any way, but are merely used as labels and/orarbitrary names to distinguish elements for ease of understanding thedisclosed examples. In some examples, the descriptor “first” may be usedto refer to an element in the detailed description, while the sameelement may be referred to in a claim with a different descriptor suchas “second” or “third.” In such instances, it should be understood thatsuch descriptors are used merely for identifying those elementsdistinctly that might, for example, otherwise share a same name. As usedherein, “approximately” and “about” refer to dimensions that may not beexact due to manufacturing tolerances and/or other real worldimperfections.

DETAILED DESCRIPTION

Methods and apparatus to provide electrical shielding for an IC packageusing a TIM are disclosed. A liquid metal thermal interface material(LM-TIM) can boost system performance of mobile PCs, gaming systems,etc. particularly when compared to traditional polymer TIMs. Compared toconventional TIMs, the thermal conductivity is 2-4 times higher inLM-TIMs for improved performance. Gallium based LM-TIM, whilehistorically implemented by end-user desktop overclocking enthusiasts,has recently become technically and economically viable in high volumemanufacturing (HVM) for computing devices (e.g., desktop, laptopcomputers, tablets, smartphones, personal computers (PCs), etc.).

However, the risk of electrical interference, such as crosstalkcoupling, signal impedance (SI), and electromagnetic interference (EMI),increases with the use of a metallic TIM. Crosstalk coupling, SI, and/orEMI can adversely affect other components on the IC package and signalsdirectly underneath the package solder mask. Additionally, the liquidnature of the metallic TIM makes it difficult to dispense and containthe TIM within an integrated circuit package. An improperly containedTIM increases the risk of electrical interference. LM-TIMs also giverise to corrosion and shorting risks. Further, the irregular extent ofLM-TIM spillage onto the package substrates utilizing micro-striprouting can also cause electrical interference problems. The abovetechnical challenges have limited the wide-spread adoption of LM-TIM. Inparticular, a solution to the risk of electrical interference isimportant due to widely-varying designs being introduced to the market.

Previous efforts have attempted to achieve consistent dispensement,application, and/or containment of LM-TIM. These efforts serve to reducethe variability in thermal performance but cannot reduce the electricalinterference risks. Electrical interference issues differ as originalequipment manufacturers (OEMs) and original design manufacturers (ODMs)differ because different OEM/ODM LM-TIM designs can differsignificantly. While there are customer-provided (e.g., postmanufacturing) shielding solutions, that can surround an IC package,such solutions fail to prevent undesirable coupling and interferencethat LM-TIM can cause within the IC package. Eliminating the use ofmicro-strip routing is another example approach for reducing electricalinterference. However, eliminating micro-strip routing cannot preventEMI and System on a Chip (SoC) immunity issues caused by undesirablecouplings among multiple dies, ungrounded thermal solutions, andexternal radio frequency (RF) noises.

Examples disclosed herein provide proper containment of LM-TIM andreduce electrical interference in an IC package by incorporatingenhanced package features such that both thermal and electrical benefitsof LM-TIM can be realized by OEMs/ODMs. Examples disclosed hereinprovide SoC immunity from external RF noises and electrostaticdischarges (ESD), and reduce (e.g., eliminate) radiated emissions fromthe SoC. Thus, examples disclosed herein are fully compliant toelectromagnetic compatibility (EMC) regulatory requirements. Examplesdisclosed herein eliminate the negative impacts of crosstalk coupling,signal impedance, and EMI.

Examples disclosed herein achieve the above benefits by utilizing thehigh electrical conductivity of LM-TIM to make the LM-TIM itself anintegral part of a die-level Faraday cage that provides a shieldingsolution internal to an associated IC package. For example, a soldermask layer separates a semiconductor die from a ground plane layer in anintegrated circuit package. The TIM surrounds the semiconductor die andis electrically coupled to the ground plane layer, thereby forming aFaraday cage that surrounds the semiconductor die. In such examples, theLM-TIM enables thermal cooling of the die while also mitigating againstundesired electromagnetic coupling and interference.

Different package features and/or designs may be implemented toelectrically tie the LM-TIM to the package ground. The particularfeatures and/or designs employed in any particular IC package dependupon the particular application for which the package is to be used.More particularly, in some examples, design choice is driven by packagesurface area. For example, the amount of area that is not occupied bydies in the SoC, surface components, stiffeners, and/or an integratedheat spreader (IHS) can determine the structural design of features ofthe package that enable the electrical coupling of a LM-TIM surroundinga die to an underlying ground plane layer.

In some examples, a first conductive layer in a package substratesupporting a die is a ground layer. In some examples, the first (ground)layer is at locations adjacent to where the LM-TIM is to be directly incontact with the package. In some examples, other signals and power arerouted on the second layer and other deeper layers, (e.g., farther awayfrom the surface of the substrate on which the die is mounted and wherethe LM-TIM is located). However, in some examples, micro-strip routingof signal and power lines can still be utilized. The ground layer beingcloser to the LM-TIM than the signal and power lines provides electricalisolation and corrosion protections for the signals and powerlines fromthe LM-TIM, which includes a gallium alloy that can include indiumand/or tin. In some examples, an array of solder resist openings (SROs)in the substrate surrounds the die(s) to be cooled with LM-TIM. Somesuch SROs include a conductive material disposed therein to enableelectrical coupling of the LM-TIM with the underlying ground planelayer. Thus, in some examples, the SROs are associated with ground padsthat are to be in contact with the LM-TIM. Such grounds pads aredistinct from ground pads used for decoupling capacitors and distinctfrom terminal pads for power and ground. In some examples, theconductive material within the SROs has a nickel finish and/or are madeof an electrically conductive adhesive (ECA) to provide protectionagainst gallium corrosion.

FIG. 1 is a plan view of an example IC package 100 constructed inaccordance with teachings disclosed herein. FIG. 2 is a cross-sectionalview of the example IC package 100 taken along line 2-2 of FIG. 1 . Asshown in the illustrated example, the IC package 100 includes asemiconductor die 102 mounted on an upper surface 200 of a packagesubstrate 106. The semiconductor die 102 is surrounded by a barrier 104that serves as a means for containing a LM-TIM 108, that fills the spacebetween the barrier 104 and the semiconductor die 102. The LM-TIM 108 isa means for dissipating heat from the semiconductor die 102.

In FIG. 1 , the LM-TIM 108 is shown with an irregular shape for purposesof illustration to represent the liquid nature of the LM-TIM 108. Inactual implementation, the volume of the LM-TIM 108 is sufficient tocompletely cover the portion of the upper surface 200 exposed betweenthe semiconductor die 102 and the barrier 104. More particularly, insome examples, the volume of the LM-TIM 108 is sufficient to not onlycover the upper surface 200 but also to fully cover or enclose thesemiconductor die 102 as represented in FIG. 2 . As with FIG. 1 , theshape of the LM-TIM 108 shown in FIG. 2 is for purposes of illustrationand not necessarily the shape the LM-TIM 108 would actually take whenfilling the space between the barrier 104 and the semiconductor die 102.More particularly, FIG. 2 shows gaps 201 above the LM-TIM 108 toindicate the volume of the LM-TIM 108 is less than the space inside thebarrier 104 and surrounding the semiconductor die 102. Using less of theLM-TIM 108 than the entire space defined within the barrier allows theLM-TIM 108 to expand when heated. In other examples, the LM-TIM 108completely fills the space within the barrier 104. While the LM-TIM 108is described as a liquid, in some examples, the LM-TIM 108 may solidifyat certain temperatures.

In the illustrated example, the package substrate 106 includes multiplelayers some of which are conductive while others are non-conductive.More particularly, in this example, the substrate 106 includes a soldermask layer 110 at the upper surface 200 of the substrate 106. Thus, inthis example, the semiconductor die 102 is mounted to and protrudes awayfrom the solder mask layer 110. The solder mask layer 110 isnon-conductive to electrically separate the semiconductor die 102 fromconductive layers of the package substrate 106, which include a groundplane layer 202 (also referred to herein as the package ground planelayer) and one or more signal and/or power line layers 204. In thisexample, the ground plane layer 202 is electrically conductive toprovide grounding for the package 100. Similarly, the signal and/orpower line layers 204 are also conductive to enable electrical routingof power and/or to provide input/output connections to components withinthe IC package 100 and/or to external pins or other connectors on theexterior of the package 100. In some examples, the package substrate 106includes multiple non-conductive layers 205 (including the solder masklayer 110) to separate different ones of the conductive layers 202, 204.In the illustrated example, the ground plane layer 202 is closer to theupper surface 200 of the substrate 106 than the other conductive layers204 are to the upper surface 200. As a result, the ground plane layer202 is closer to the die 102 (and associated LM-TIM 108) than the otherconductive layers 204 are to the die 102 (and associated LM-TIM 108),thereby providing electrical isolation to the die 102 (and associatedLM-TIM 108) from the other conductive layers 204.

In the illustrated example, the semiconductor die 102 is mounted orattached to the upper surface 200 of the substrate 106 (e.g., the soldermask layer 110) with a die epoxy 112 that surrounds a perimeter of thesemiconductor die 102. Additionally or alternatively, in some examples,the die epoxy 112 is applied between the interfacing surfaces of thesemiconductor die 102 and the solder mask layer 110.

In some examples, the LM-TIM 108 fully envelopes and/or encloses thesemiconductor die 102 on all surfaces of the die 102 extending above thesolder mask layer 110. Additionally or alternatively, the LM-TIM 108 mayenclose more than one semiconductor die 102 in one or more containmentbarriers 104. FIG. 1 illustrates an example wherein there is one die102. In other examples, more than one die 102 may be included in the ICpackage 100. Further, ones of the multiple dies may be enclosed in thesame TIM and/or distinct portions of TIM in separate containmentbarriers.

In some examples, the IC package 100 includes a cold plate 206 (alsoreferred to herein as a heat spreader) that attaches to an upper surfaceof the barrier 104 so as to enclose the space within the barrier 104filled with the LM-TIM 108. Thus, the cold plate 206 also serves asmeans for containing the LM-TIM 108. In the illustrated example of FIG.1 , the cold plate 206 is omitted to better illustrate the othercomponents of the example IC package 100 in the plan view.

In some examples, the IC package 100 includes a metal stiffener 114positioned adjacent an exterior perimeter of the package 100 to providerigidity and strength to the package. The size of the stiffener 114 andthe relative spacing of the stiffener 114 and the barrier 104 dependsupon the particular design and/or size of the IC package 100. In thisexample, the stiffener 114 is spaced apart and distinct from the barrier104 and made of metal. Further, in this example, the barrier 104 is madeof a non-conductive material (e.g., filled or unfilled siliconepolymers, foams, polymeric rubbers etc.) to electrically isolate theLM-TIM 108 that interfaces with inner surfaces of the barrier 104. Inother examples, the barrier 104 is made of a conductive material (e.g.,metal). In such examples, the barrier 104 remains electrically isolatedfrom other components (e.g., the stiffener 114) due to the spacingbetween the barrier 104 and the stiffener 114.

While the barrier 104 and the non-conductive solder mask layer 110electrically isolate the LM-TIM 108 from the other components of the ICpackage 100, the LM-TIM 108 is still electrically coupled to the groundplane layer 202. More particularly, in the illustrated example of FIGS.1 and 2 , one or more solder resist openings (SROs) 116 (furtherdetailed in FIG. 3 ), such as apertures, for example, extend throughopposing surfaces of the solder mask layer 110 and are filled with aconductive material 118 electrically coupling the ground plane layer 202below the solder mask layer 110 with the LM-TIM 108 above the soldermask layer 110. Fully surrounding or enclosing the semiconductor die 102with the LM-TIM 108 and electrically coupling the LM-TIM 108 with theground plane layer 202 enables the LM-TIM 108 to serves as a Faradaycage that provides die-level shielding for the die 102 internal to theIC package 100. As a result, examples disclosed herein provide robustSoC immunity from external RF noises and electro-static discharges.Further, the grounded LM-TIM 108 reduces (e.g., eliminates) radiatedemissions from the SoC, thereby enabling compliance with EMC regulatoryrequirements.

The conductive material 118 is a means for conducting electricitythrough the SROs 116. In some examples, the conductive material 118 maybe the same material as used for the ground plane layer 202 (e.g.,copper). Additionally or alternatively, in some examples, the conductivematerial 118 is the same material as the LM-TIM 108. That is, in someexamples, when the LM-TIM 108 is applied around the semiconductor die102, the LM-TIM 108 extends into and fills the SROs 116 to contactexposed portions of the underlying ground plane layer 202.

In some examples, the LM-TIM 108 includes gallium. More particularly, insome examples, the LM-TIM 108 is a gallium alloy that includes indiumand/or tin. Gallium can be corrosive to the copper used for the groundplane layer 202. Accordingly, in some examples, the conductive material118 is a material distinct from both the ground plane layer 202 and theLM-TIM 108 that is resistant to gallium corrosion. Specifically, in someexamples, the conductive material 118 has a nickel finish and/or anickel-gold finish. In other examples, the conductive material 118 is anelectrically conductive epoxy adhesive (ECA).

In this example, multiple SROs 116 are arranged in an array distributedaround the semiconductor die 102 at a location between the outersurfaces of the die 102 and the inner surfaces of the barrier 104. Inthe example illustrated of FIG. 1 , the multiple SROs 116 are positionedin straight lines parallel to the barrier 104. In some examples, themultiple SROs 116 are positioned in a circular pattern, a randompattern, or any other suitable arrangement throughout the locationbetween the outer surfaces of the die 102 and the inner surfaces of thebarrier 104. In the example of FIG. 1 , the SROs 116 are square-shaped.In other examples, each of the SROs 116 can be any shape, such ascircular, triangular, rectangular, etc. In some examples, each of theSROs 116 are approximately the same size and have the same dimensions.In some examples, the particular size of the SROs 116 can depend uponthe design and available spacing in the IC package 100. Thus, in someexamples, the SROs 116 may be larger or smaller (relative to othercomponents) than what is shown in the illustrated example. In otherexamples, the array of SROs 116 can include multiple SROs 116 ofdifferent dimensions and/or sizes. In some examples, the total number ofSROs 116 can be more and/or less than the total number of SROs 116illustrated in FIG. 1 . Further, in some examples, rather than discreteopenings, the SROs 116 may correspond to one or more elongated trenchesextending some or all of the length of a side of the die 102. In someexamples, a single trench may extend the entire way around the die 102and be filled with the conductive material 118 to electrically couplethe LM-TIM 108 with the ground plane layer 202.

FIG. 3 is an enlarged view of a portion of the example IC package 100 ofFIG. 1 corresponding to region A shown in FIG. 2 . In this example,region A illustrates an example SRO 116 that extends through the soldermask layer 110 and is filled with a conductive material 118 electricallycoupling the ground plane layer 202 below the solder mask layer 110 withthe LM-TIM 108 above the solder mask layer 110.

As shown in the illustrated example of FIG. 3 , the conductive material118 fills part of the SRO 116 (e.g., aperture) in the solder mask layer110 such that the conductive material 118 has a thickness that is lessthan the thickness of the solder mask layer 110. In other examples, theconductive material 118 extends above the upper surface 200 of thesolder mask layer 110 such that the conductive material 118 has athickness that is more than the thickness of the solder mask layer 110.In some examples, different ones of the multiple SROs 116 in an exampleIC package 100 can vary in thickness and/or conductive material (e.g.nickel finish, nickel-gold finish, and/or conductive epoxy adhesive).

FIG. 4 is a plan view of another example IC package 400 constructed inaccordance with teachings disclosed herein. FIG. 5 is a cross-sectionalview of the example IC package 400 taken along line 5-5 of FIG. 4 . Theexample IC package 400 of FIGS. 4 and 5 is similar to the example ICpackage 100 of FIGS. 1-3 except for the location of the solder resistopenings (SROs) 116 and the corresponding conductive material 118disposed therein. Specifically, in the illustrated example of FIGS. 4and 5 , the SROs 116 and associated conductive material 118 are alignedwith and underneath the containment barrier 104. As a result, in thisexample, the LM-TIM 108 is electrically coupled with the ground planelayer 202 through the conductive material 118 indirectly via thecontainment barrier 104. Accordingly, in this example, the containmentbarrier 104 is electrically conductive and forms part of the Faradaycage (along with the LM-TIM 108) surrounding the semiconductor die 102to mitigate against electrical interference. In some examples, thematerial of the barrier 104 is made of conductive polymeric materials(e.g., silver filled epoxy, nickel-graphite/silicone polymer,titanium-nickel-carbon composite, etc.) and/or conductive foams (e.g.,closed cell foam, open cell foam, etc.). In some such examples, thematerial used for the barrier 104 is dispensed using an automaticcontrol machine. In other examples, the containment barrier 104 islaser-cut or die-cut from a sheet of material and/or created using oneor more gasket materials (e.g., packaged in rolls) that can be formed ina variety of cross-section shapes. Such materials can include simplepolymeric rubbers, foams, thermal pads, or gasket materials.

In the example IC package 400, multiple SROs 116 are arranged in anarray distributed at a location within the solder mask layer 110 alignedwith the containment barrier 104. Positioning the SROs 116 in alignmentwith the barrier 104 enables the barrier 104 to be positioned closer tothe semiconductor die 102 than in the illustrated example of FIGS. 1-3in which space is needed for the SROs 116 between the barrier 104 andthe semiconductor die 102. This is a beneficial option when spatialconstraints are a limited design factor for a particular IC package. Inthe illustrated example of FIG. 4 , the multiple SROs 116 are positionedin a straight line parallel to and positioned between the outer surfaceand inner surface of the barrier 104. In other examples, the SROs 116are positioned in any other suitable pattern or arrangement. In someexamples, separate SROs 116 (other than those aligned with the barrier104) are located between the barrier 104 and the die 102 (e.g., similarto what is shown in FIGS. 1-3 ) to enable the direct electrical couplingof the LM-TIM 108 with the ground plane layer 202 in addition to theindirect coupling via the conductive barrier 104. Additionally oralternatively, in some examples, the SROs 116 are positioned and/ordimensioned to be partially under the barrier 104 and to partiallyextend inward of the inner surface of the barrier 104 toward the die102.

FIG. 6 is a plan view of another example IC package 600 constructed inaccordance with teachings disclosed herein. FIG. 7 is a cross-sectionalview of the example IC package 600 taken along line 7-7 of FIG. 6 . Theexample IC package 600 of FIGS. 6 and 7 , is similar to the example ICpackage 400 of FIGS. 4 and 5 except that the IC package 600 of FIGS. 6and 7 includes a stiffener 602 that also serves as a means forcontaining the LM-TIM 108 (e.g., instead of the barrier 104 shown inFIGS. 4 and 5 ). Further, the example IC package 600 of FIGS. 6 and 7differs from the example IC package 400 of FIGS. 4 and 5 based on thelocation of the solder resist openings (SROs) 116 and the correspondingconductive material 118 disposed therein. Specifically, in theillustrated example of FIGS. 6 and 7 , the SROs 116 and associatedconductive material 118 are aligned with and underneath the metalstiffener 602, which has a larger dimension than the stiffener 114 inFIGS. 4 and 5 . As with the stiffener 114 in the previous examples, thestiffener 602 of FIGS. 6 and 7 is made of metal and, therefore,electrically conductive. As a result, in this example, the LM-TIM 108 iselectrically coupled with the ground plane layer 202 through theconductive material 118 indirectly via the metal stiffener 602. In suchexamples, the stiffener 602 forms part of the Faraday cage (along withthe LM-TIM 108) surrounding the semiconductor die 102 to mitigateagainst electrical interference. In some examples, a conductive adhesivecan be used to attach the metal stiffener 602 to the substrate 106 toprovide mechanical flexibility and strength that can withstandmechanical stresses resulting from coefficient of thermal expansion(CTE) mismatch effects. Further, the conductive adhesive ensures areliable (e.g., relatively low ohmic) contact with the ground planelayer 202.

In this example IC package 600, multiple SROs 116 are arranged in afirst array distributed at a location within the solder mask layer 110aligned with the metal stiffener 602 and encircling the semiconductordie 102. Additionally or alternatively, a second array of multiple SROs116 are distributed to encircle both the first array of multiple SROs116 and the semiconductor die 102. In some examples, a second array ofmultiple SROs 116 may be needed to provide sufficient grounding contactfor the example IC package 600. That is, in some examples, the numberand/or size of the SROs 116 is selected so that the stiffener 602 makesrelatively low ohmic contact with the ground plane layer 202. Further,in some examples, the separate arrays or rings of SROs 116 serve toreduce (e.g., prevent) electrical interference, particularly in exampleswhere the stiffener 602 is relatively large. For instance, if the widthof the stiffener 602 is comparable to or larger than about one fourth ofa wavelength of the highest expected radio frequency (e.g.,approximately 5 mm for a frequency of 7.125 GHz), then two rings orarrays of the SROs 116 may be implemented for more robust protectionagainst electrical interference. For a stiffener 602 with a width ofless than 2.5 mm, a single array or ring of SROs 116 may be adequate.

While two arrays of SROs 116 are shown in the illustrated example, inother examples, any number of arrays of multiple SROs 116 may be used toprovide sufficient grounding contact for the example IC package 600. Inthe example illustrated of FIG. 6 , the multiple SROs 116 are positionedin straight lines parallel to and positioned between the outer surfaceand inner surface of the metal stiffener 602. In some examples, themultiple SROs 116 are positioned in a circular pattern, a randompattern, or any other suitable arrangement throughout the locationcorresponding to the area within the outer surface and inner surface ofthe metal stiffener 602. In some examples, separate SROs 116 withassociated conductive material 118 are located between the stiffener 114and the die 102 (e.g., similar to what is shown in FIGS. 4 and 5 ) toenable to direct electrical coupling of the LM-TIM 108 with the groundplane layer 202 in addition to the indirect coupling via the stiffener602. Additionally or alternatively, in some examples, the SROs 116 arepositioned and/or dimensioned to be partially under the stiffener 602and to partially extend inward of the inner surface of the stiffener 602toward the die 102.

Another distinction between the example IC package 600 of FIGS. 6 and 7and the IC package 400 of FIGS. 4 and 5 is the structure of the groundplane layer 202. Specifically, as shown in FIG. 5 , the electricallyconductive material of the ground plane layer 202 in the example ICpackage 400 extends across IC package 400 underneath the semiconductordie 102. As explained above, the semiconductor die 102 in the IC package400 of FIGS. 4 and 5 is separated from the ground plane layer 202 by thesolder mask layer 110. By contrast, the electrically conductive materialof the ground plane layer 202 in the example IC package 600 of FIGS. 6and 7 does not pass directly underneath the semiconductor die 102. Theparticular design and/or structure of the ground plane layer 202 doesnot affect the ability of the LM-TIM 108 to form a Faraday cage aroundthe semiconductor die 102 to mitigate against electrical interference.Thus, the structure of the example ground plane layer 202 shown in FIG.7 could alternatively be implemented in the IC package 100 of FIGS. 1-3and/or in the IC package 400 of FIGS. 4 and 5 . Likewise, the structureof the example ground plane layer 202 shown in FIGS. 2 and 5 couldalternatively be implemented in the IC package 600 of FIGS. 6 and 7 .Further, the structure of the ground plane layer 202 in any examplesdisclosed herein may partially extend underneath the semiconductor die102 without extending the entire way across.

FIG. 8 is a cross-sectional view of another example IC package 800similar to the example IC package 600 shown in FIG. 7 . The example ICpackage 800 of FIG. 8 differs from the example IC package 600 of FIG. 6in that the IC package 800 of FIG. 8 includes an integrated heatspreader (IHS) 802 (also referred to herein as a package lid) structuredto serve as a means for containing the LM-TIM 108 around thesemiconductor die 102 (e.g., instead of the stiffener 602 and separatecold plate 206 as shown in FIG. 7 ). In this example, the integratedheat spreader 802 is electrically conductive. As a result, in thisexample, the LM-TIM 108 is electrically coupled with the ground planelayer 202 through the conductive material 118 indirectly via the IHS 802such that the IHS 802 becomes part of the Faraday cage (along with theLM-TIM 108) that surrounds the die 102 to mitigate against electricalinterference.

In some examples, the SROs 116 and associated conductive material 118 isarranged to electrically couple the integrated heat spreader 802 to theground plane layer 202 in a similar manner as the SROs 116 describedabove in connection with FIGS. 6 and 7 . Further, as described above,while the ground plane layer 202 in FIG. 8 is shown similar to theground plane layer 202 in FIG. 7 , the structure of the ground planelayer 202 may be modified in any suitable manner (e.g., similar to theground plane layer 202 as shown in FIGS. 2 and 5 ).

As used herein, the phrase “in communication,” including variationsthereof, encompasses direct communication and/or indirect communicationthrough one or more intermediary components, and does not require directphysical (e.g., wired) communication and/or constant communication, butrather additionally includes selective communication at periodicintervals, scheduled intervals, aperiodic intervals, and/or one-timeevents.

“Including” and “comprising” (and all forms and tenses thereof) are usedherein to be open ended terms. Thus, whenever a claim employs any formof “include” or “comprise” (e.g., comprises, includes, comprising,including, having, etc.) as a preamble or within a claim recitation ofany kind, it is to be understood that additional elements, terms, etc.may be present without falling outside the scope of the correspondingclaim or recitation. As used herein, when the phrase “at least” is usedas the transition term in, for example, a preamble of a claim, it isopen-ended in the same manner as the term “comprising” and “including”are open ended. The term “and/or” when used, for example, in a form suchas A, B, and/or C refers to any combination or subset of A, B, C such as(1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) Bwith C, and (7) A with B and with C. As used herein in the context ofdescribing structures, components, items, objects and/or things, thephrase “at least one of A and B” is intended to refer to implementationsincluding any of (1) at least one A, (2) at least one B, and (3) atleast one A and at least one B. Similarly, as used herein in the contextof describing structures, components, items, objects and/or things, thephrase “at least one of A or B” is intended to refer to implementationsincluding any of (1) at least one A, (2) at least one B, and (3) atleast one A and at least one B. As used herein in the context ofdescribing the performance or execution of processes, instructions,actions, activities and/or steps, the phrase “at least one of A and B”is intended to refer to implementations including any of (1) at leastone A, (2) at least one B, and (3) at least one A and at least one B.Similarly, as used herein in the context of describing the performanceor execution of processes, instructions, actions, activities and/orsteps, the phrase “at least one of A or B” is intended to refer toimplementations including any of (1) at least one A, (2) at least one B,and (3) at least one A and at least one B.

As used herein, singular references (e.g., “a”, “an”, “first”, “second”,etc.) do not exclude a plurality. The term “a” or “an” entity, as usedherein, refers to one or more of that entity. The terms “a” (or “an”),“one or more”, and “at least one” can be used interchangeably herein.Furthermore, although individually listed, a plurality of means,elements or method actions may be implemented by, e.g., a single unit orprocessor. Additionally, although individual features may be included indifferent examples or claims, these may possibly be combined, and theinclusion in different examples or claims does not imply that acombination of features is not feasible and/or advantageous.

From the foregoing, it will be appreciated that example methods,apparatus and articles of manufacture have been disclosed that utilizethe high electrical conductivity of LM-TIM to make the LM-TIM itself anintegral part of a die-level Faraday cage that provides a shieldingsolution internal to an associated IC package for one or moresemiconductor dies while also serving as a means for dissipating heatfrom dies.

Example 1 includes an integrated circuit (IC) package comprising asubstrate including a ground plane layer and a solder mask layer, asemiconductor die attached to the substrate, the solder mask layerseparating the semiconductor die from the ground plane layer, and athermal interface material (TIM) surrounding at least a portion of thesemiconductor die, the TIM electrically coupled to the ground planelayer.

Example 2 includes the IC package as defined in example 1, wherein thesolder mask layer includes an aperture extending therethrough, the TIMelectrically coupled to the ground plane layer via the aperture.

Example 3 includes the IC package as defined in example 2, furtherincluding a conductive material in the aperture to electrically couplethe TIM and the ground plane layer, the conductive material differentthan the TIM and different than a material of the ground plane layer.

Example 4 includes the IC package as defined in example 3, wherein theTIM is a liquid metal thermal interface material.

Example 5 includes the IC package as defined in example 4, wherein theliquid metal thermal interface material includes gallium.

Example 6 includes the IC package as defined in example 3, wherein theconductive material includes at least one of nickel or gold.

Example 7 includes the IC package as defined in example 3, wherein theconductive material is a conductive epoxy adhesive.

Example 8 includes the IC package as defined in example 2, furtherincluding a containment barrier for the TIM that is electricallynon-conductive and spaced apart from the semiconductor die, the apertureextending through the solder mask layer at a location between facingsurfaces of the containment barrier and the semiconductor die.

Example 9 includes the IC package as defined in example 2, wherein thesolder mask layer includes multiple apertures arranged in an arraydistributed around the semiconductor die, the TIM electrically coupledto the ground plane layer through the multiple apertures.

Example 10 includes the IC package as defined in example 9, wherein thearray is a first array, ones of the multiple apertures arranged in asecond array different than the first array, the ones of the multipleapertures in the second array distributed to surround the semiconductordie, the first array closer to the semiconductor die than the secondarray.

Example 11 includes the IC package as defined in example 9, wherein theTIM is to fully envelope the semiconductor die adjacent the substrate,the TIM electrically coupled to the ground plane layer to create aFaraday cage surrounding the semiconductor die.

Example 12 includes the IC package as defined in example 1, furtherincluding a containment barrier spaced apart from and surrounding thesemiconductor die, the TIM to fill a space between the containmentbarrier and the semiconductor die.

Example 13 includes the IC package as defined in example 12, furtherincluding a conductive material that extends through the solder masklayer to electrically couple the containment barrier and the groundplane layer, the TIM electrically coupled to the ground plane layer viathe containment barrier and the conductive material.

Example 14 includes the IC package as defined in example 13, wherein theconductive material extends through the solder mask layer via aplurality of spaced apart apertures extending through the solder masklayer, the plurality of spaced apart apertures including (1) a firstarray of apertures encircling the semiconductor die and (2) a secondarray of apertures encircling both the semiconductor die and the firstarray of apertures.

Example 15 includes the IC package as defined in example 12, wherein thecontainment barrier is a metal package stiffener.

Example 16 includes the IC package as defined in example 12, wherein thecontainment barrier is an integrated heat spreader (IHS).

Example 17 includes an integrated circuit (IC) package comprising asolder mask layer having opposing first and second surfaces, asemiconductor die adjacent the first surface, a ground plane layeradjacent the second surface, and a TIM in contact with the first surfaceof the solder mask layer and exterior surfaces of the semiconductor die,the TIM electrically coupled to the ground plane layer.

Example 18 includes the IC package as defined in example 17, wherein thesolder mask layer includes an aperture extending therethrough betweenthe first and second surface, the TIM electrically coupled to the groundplane layer via the aperture.

Example 19 includes the IC package as defined in example 18, furtherincluding a conductive material disposed in the aperture to electricallycouple the TIM and the ground plane layer.

Example 20 includes the IC package as defined in example 19, wherein theTIM is a liquid metal thermal interface material.

Example 21 includes the IC package as defined in example 20, wherein theTIM includes gallium, and the conductive material is different than theTIM and different than a material of the ground plane layer to resistgallium corrosion.

Example 22 includes the IC package as defined in example 21, wherein theconductive material includes at least one of nickel or gold.

Example 23 includes the IC package as defined in example 21, wherein theconductive material includes a conductive epoxy adhesive.

Example 24 includes the IC package as defined in example 19, wherein theconductive material extends through the solder mask layer via aplurality of spaced apart apertures extending through the solder masklayer, the plurality of spaced apart apertures distributed (1) in afirst ring encircling the semiconductor die and (2) in a second ringencircling both the semiconductor die and the first ring.

Example 25 includes the IC package as defined in example 19, furtherincluding a containment barrier that is electrically non-conductive andspaced apart from the conductive material, the conductive materialextending through the solder mask layer at a location between thecontainment barrier and the semiconductor die.

Example 26 includes the IC package as defined in example 17, wherein thesolder mask layer includes multiple apertures extending therethrough,ones of the multiple apertures arranged in a ring to surround thesemiconductor die, the TIM electrically coupled to the ground planelayer through the multiple apertures.

Example 27 includes the IC package as defined in example 26, wherein thering is a first ring, ones of the multiple apertures arranged in asecond ring different than the first ring, the ones of the multipleapertures in the second ring to surround the semiconductor die, thefirst ring closer to the semiconductor die than the second ring.

Example 28 includes the IC package as defined in example 26, wherein theTIM is to fully enclose the semiconductor die adjacent a first side ofthe solder mask layer, the TIM electrically coupled to the ground planelayer to create a Faraday cage surrounding the semiconductor die.

Example 29 includes the IC package as define in example 17, furtherincluding a containment barrier spaced apart from and surrounding thesemiconductor die, the TIM disposed between the containment barrier andthe semiconductor die.

Example 30 includes the IC package as defined in example 29, furtherincluding a conductive material extending through the solder mask layerto electrically couple the containment barrier to the ground planelayer, the TIM electrically coupled to the ground plane layer via thecontainment barrier.

Example 31 includes the IC package as defined in example 29, furtherincluding a package stiffener that is spaced apart from the containmentbarrier, the containment barrier between the semiconductor die and thepackage stiffener.

Example 32 includes the IC package as defined in example 29, wherein thecontainment barrier is an integrated heat spreader (IHS).

Example 33 includes an integrated circuit (IC) package comprising asemiconductor die, a ground plane layer, a solder mask layer disposedbetween the ground plane layer and the semiconductor die, and means fordissipating heat from the semiconductor die, the heat dissipating meansto be in contact with exterior surfaces of the semiconductor dieprotruding away from the solder mask layer, the heat dissipating meanselectrically coupled to the ground plane layer.

Example 34 includes the IC package as defined in example 33, furtherincluding an opening in the solder mask layer, the heat dissipatingmeans electrically coupled to the ground plane layer through theopening.

Example 35 includes the integrated circuit (IC) package as defined inexample 34, further including means for conducting electricity throughthe opening in the solder mask layer, the electricity conducting meansto electrically couple the heat dissipating means to the ground planelayer.

Example 36 includes the integrated circuit (IC) package as defined inexample 33, further including means for containing the heat dissipatingmeans, the containing means spaced apart from and surrounding thesemiconductor die, the heat dissipating means to fill a space betweenthe containing means and the semiconductor die.

Example 37 includes the IC package as defined in example 36, wherein thecontaining means is electrically conductive and electrically coupled tothe ground plane layer, the heat dissipating means electrically coupledto the ground plane layer via the containing means.

Example 38 includes the IC package as defined in example 37, wherein thecontaining means is a metal package stiffener.

Example 39 includes the IC package as defined in example 37, wherein thecontaining means is a package lid of the IC package.

Example 40 includes the IC package as defined in example 37, wherein thecontaining means is an electrically conductive foam barrier.

Example 41 includes the IC package as defined in example 36, wherein thecontaining means is electrically non-conductive and spaced apart fromthe semiconductor die, the heat dissipating means electrically coupledto the ground plane layer via an opening in the solder mask layerbetween the containing means and the semiconductor die.

Example 42 includes the IC package as defined in example 34, wherein theheat dissipating means is to fully cover the semiconductor die adjacentthe solder mask layer to create a Faraday cage around the semiconductordie.

Example 43 includes the IC package as defined in example 34, furtherincluding multiple openings distributed in the solder mask layer tosurround the semiconductor die, the heat dissipating means electricallycoupled to the ground plane layer through the multiple openings. the ICpackage as defined in example 43, wherein a first set of the multipleopenings are associated with a first array of openings, a second set ofthe openings are associated with a second array of openings differentthan the first array of openings, the second array of openings tosurround the semiconductor die, the first array of openings closer tothe semiconductor die than the second array of openings.

Although certain example methods, apparatus and articles of manufacturehave been disclosed herein, the scope of coverage of this patent is notlimited thereto. On the contrary, this patent covers all methods,apparatus and articles of manufacture fairly falling within the scope ofthe claims of this patent.

The following claims are hereby incorporated into this DetailedDescription by this reference, with each claim standing on its own as aseparate embodiment of the present disclosure.

What is claimed is:
 1. An integrated circuit (IC) package comprising: asubstrate including a ground plane layer and a solder mask layer, thesolder mask layer including an aperture extending therethrough; asemiconductor die attached to the substrate, the solder mask layerseparating the semiconductor die from the ground plane layer; a thermalinterface material (TIM) surrounding at least a portion of thesemiconductor die; and a conductive material in the aperture, the TIMelectrically coupled to the ground plane layer via the conductivematerial, the conductive material different than the TIM and differentthan a material of the ground plane layer.
 2. The IC package as definedin claim 1, wherein the TIM is a liquid metal thermal interfacematerial.
 3. The IC package as defined in claim 2, wherein the liquidmetal thermal interface material includes gallium.
 4. The IC package asdefined in claim 1, wherein the conductive material includes at leastone of nickel or gold.
 5. The IC package as defined in claim 1, whereinthe conductive material is a conductive epoxy adhesive.
 6. The ICpackage as defined in claim 1, wherein the solder mask layer includesmultiple apertures arranged in an array distributed around thesemiconductor die, the TIM electrically coupled to the ground planelayer through the multiple apertures.
 7. The IC package as defined inclaim 6, wherein the array is a first array, ones of the multipleapertures arranged in a second array different than the first array, theones of the multiple apertures in the second array distributed tosurround the semiconductor die, the first array closer to thesemiconductor die than the second array.
 8. The IC package as defined inclaim 6, wherein the TIM fully envelopes a perimeter of thesemiconductor die adjacent the substrate, the TIM electrically coupledto the ground plane layer to create a Faraday cage surrounding thesemiconductor die.
 9. The IC package as defined in claim 1, furtherincluding a containment barrier spaced apart from and surrounding thesemiconductor die, the TIM to filling a space between the containmentbarrier and the semiconductor die.
 10. The IC package as defined inclaim 9, wherein the conductive material is electrically coupled to thecontainment barrier and the ground plane layer, the TIM electricallycoupled to the ground plane layer via the containment barrier and theconductive material.
 11. The IC package as defined in claim 10, whereinthe aperture is one of a plurality of spaced apart apertures extendingthrough the solder mask layer, the plurality of spaced apart aperturesincluding (1) a first array of apertures encircling the semiconductordie and (2) a second array of apertures encircling both thesemiconductor die and the first array of apertures.
 12. The IC packageas defined in claim 9, wherein the containment barrier is a metalpackage stiffener.
 13. The IC package as defined in claim 9, wherein thecontainment barrier is an integrated heat spreader (IHS).
 14. Anintegrated circuit (IC) package comprising: a substrate including aground plane layer and a solder mask layer; a semiconductor die attachedto the substrate, the solder mask layer separating the semiconductor diefrom the ground plane layer; a thermal interface material (TIM)surrounding at least a portion of the semiconductor die, the TIMelectrically coupled to the ground plane layer; and a containmentbarrier for the TIM that is electrically non-conductive and spaced apartfrom the semiconductor die, an aperture extending through the soldermask layer at a location between facing surfaces of the containmentbarrier and the semiconductor die.
 15. An integrated circuit (IC)package comprising: a solder mask layer having opposing first and secondsurfaces, the solder mask layer including an aperture extendingtherethrough between the first and second surfaces; a semiconductor dieadjacent the first surface; a ground plane layer adjacent the secondsurface; a TIM in contact with the first surface of the solder masklayer and exterior surfaces of the semiconductor die; a conductivematerial disposed in the aperture, the TIM electrically coupled to theground plane layer via the conductive material; and a containmentbarrier that is electrically non-conductive and spaced apart from theconductive material, the conductive material extending through thesolder mask layer at a location between the containment barrier and thesemiconductor die.
 16. The IC package as defined in claim 15, whereinthe conductive material extends through the solder mask layer via aplurality of spaced apart apertures extending through the solder masklayer, the plurality of spaced apart apertures distributed (1) in afirst ring encircling the semiconductor die and (2) in a second ringencircling both the semiconductor die and the first ring.
 17. The ICpackage as defined in claim 15, wherein the TIM is disposed between thecontainment barrier and the semiconductor die.
 18. The IC package asdefined in claim 17, further including a package stiffener that isspaced apart from the containment barrier, the containment barrierbetween the semiconductor die and the package stiffener.
 19. Anintegrated circuit (IC) package comprising: a semiconductor die; aground plane layer; a solder mask layer disposed between the groundplane layer and the semiconductor die; means for dissipating heat fromthe semiconductor die, the heat dissipating means contacting exteriorsurfaces of the semiconductor die protruding away from the solder masklayer; and means for containing the heat dissipating means, thecontaining means being non-conductive and spaced apart from thesemiconductor die, the heat dissipating means filling a space betweenthe containing means and the semiconductor die, the heat dissipatingmeans electrically coupled to the ground plane layer via an opening inthe solder mask layer between the containing means and the semiconductordie.
 20. The integrated circuit (IC) package as defined in claim 19,wherein the containing means surrounds the semiconductor die.
 21. The ICpackage as defined in claim 20, wherein the containing means iselectrically conductive and electrically coupled to the ground planelayer, the heat dissipating means electrically coupled to the groundplane layer via the containing means.
 22. The IC package as defined inclaim 21, wherein the containing means is a package lid of the ICpackage.
 23. The IC package as defined in claim 21, wherein thecontaining means is an electrically conductive foam barrier.
 24. The ICpackage as defined in claim 19, wherein the heat dissipating means is tofully cover the semiconductor die adjacent the solder mask layer tocreate a Faraday cage around the semiconductor die.
 25. The IC packageas defined in claim 19, further including multiple ones of the openingdistributed in the solder mask layer to surround the semiconductor die,the heat dissipating means electrically coupled to the ground planelayer through the multiple ones of the opening.